View S1S65010_7414682.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

S1S65010 seiko epson corporation network camera controller with jpeg encoder ? descriptions S1S65010 is an optimum network camera controller ic for conf iguring internet cameras. in addition to network/protocol process function, it also has came ra interface and jpeg encoder function. connecting a flash rom stored with a camera module, phy for ethernet and firmware to the S1S65010 enables simple configuration of the internet camera. image capturing from cameras and jpeg encoding is executed at the receipt of shutter command from a client. when the S1S65010 is operated as an http serv er on the lan, it sends image files to the cli ent upon request. capturing images and sending them to the designated client can be done full time, or at a constant frequency using internal timer, or at a trigger on an interrupt pin using external sensors or other device. images can be sent as an attachment to the e-mail. S1S65010, equipped with gpio and i 2 c bus, can configure cameras and control ex ternal devices such as a motor via these ports through the network. a sample software is supplied with this product. ? features z enables the function of the in ternet camera without pc z compatible with s1s65000 pins. software upper compatible with s1s65000. z realizes 30fps@vga frame rate as a network camera. z works with a variety of camera modules up to 2 mega pixels (approx. 2 million pixels). z supports i 2 s for voice/audio data. z compresses images in jpeg format with har dware jpeg encoder (complies with iso 10918) z can configure various cont rol settings via the network z can send images via e-mail z can save power consumption by using wake-up mode t hat changes status of star t, shoot and pause on a regular cycle. z has a compact flash interface for a cf memory card or a wireless lan interface (802.11b/g). z one-chip solution, which can reduce system cost. z arm720t rev 4.3 is built-in (with 8kb cache) 50mhz ? built-in functions z cpu: x 32bit risc arm720t (50mhz) x 32bit-long codes and efficient 16bit-long codes (thumb code) can be selected for use x 31 general-purpose 32 bit registers x a multiplier is included in the cpu. z ram: x 78kb embedded ram for cpu/jpeg/ethernet work z camera input/jpeg encoder: x 8 bit parallel interface yuv4-2-2 input x resolution up to approx. 1600 1200 (uxga, sxga, xga, vga, qvga, cif, qcif) x supports itu-r bt656 format x hardware jpeg encoder x max. 30 fps @vga, 30 fps @cif x maximum pixel clock frequency for camera data input: less than 2/3 of cpu clock z jpeg: x hardware jpeg encoder x resize function x dedicated line buffer x variable volume fifo for jpeg encoder output x an enhanced dma z network: x ethernet mac controller supporting 10/100 base full duplex and half duplex mode x media independent interf ace (ieee 802.3 clause 22 compliant) x an enhanced dma z external memory controller: x 16 bit data bus x supports 2 to 128 mb sdram x supports static memory (flash eeprom/sram) (maximum capacity : 16mb) x 3 chip select pins (typically for sdram, flash rom and another chip). z cf card interface: x cf+ specification rev.1.4 compliant. x usable as an interface for wireless lan, phs card, etc x supports true ide mode z standby function: x the halt function to stop the cpu clock when cpu operation is not required. x programmable i/o clock stop function for major i/o block clocks. z timer, watchdog timer: x 16-bit timer 3 channels x re-load/cyclic or one shot operation mode x supports toggle outputs from timer underflow or port outputs. x interrupt output or re-settable watchdog timer.
S1S65010 2 epson z serial interface: x uart: 16550 software compatible 1channel x uart lite: 16550 software downward compatible (limited function) 1channel x spi: clock synchronous type 1 channel x i 2 c master interface (camera interface and general-purpose use) x i 2 s interface 2 channels (audio support, i 2 s standard compliant) z interrupt controller: x supports 32 irqs and 2 fiqs. z real time clock: x supports day, hour, minute and second. x the internal timer tap from 1/128 to 1/2 can be used as the interrupt source x supports alarm function and interrupt. z gpio: x general-purpose i/o port (up to 57 ports) directions programmable for all ports. x some ports are shared with other i/o functions. z power supply: x 3.3v (i/o power supply) x 1.8v (core power supply) x 1.8v (analog power supply for pll) x 2.4v (min.) - 3.6v (max.) (camera i/o power supply) z package: x tqfp 144 pin (tqfp24) 16 16 1 mm 0.4mm pin pitch ? supporting protocols arp, icmp, ip, tcp, udp, httpd, sm tp, dhcp, ftp, dns resolver, telnet necessary protocols can be added or updated by rewriting flash rom. addition or update by the cust omer is also possible. protocols are prepared as epson?s samp le software or partner?s products. ? block diagram S1S65010 arm720t rtc wdt uart i 2 c spi eeprom gpio cf card interface intc timer internal sram camera interface resize & line buf jpeg w/fifo & dma 10/100 ethermac w/fifo camera module ethernet phy flash rom sdram memc uart i 2 c gpio cf card interfface dmac1 i 2 s i 2 s uart lite uart lite
S1S65010 epson 3 ? pin assignment pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1 ma14 37 md12 73 trst# 109 cmdata5 2 ma15 38 md13 74 tck 110 cmdata6 3 ma16 39 md14 75 tms 111 cmdata7 4 ma17 40 md15 76 tdi 112 vss 5 ma18 41 mdqml 77 tdo 113 lvdd 6 vss 42 mdqmh 78 vss 114 gpiod0 7 ma19 43 hvdd1 79 gpioa0 115 gpiod1 8 mcs2# 44 vss 80 gpioa1 116 cfce2# 9 mcs1# 45 mii_crs 81 gpioa2 117 cfce1# 10 mcs0# 46 mii_col 82 gpioa3 118 cfiord# 11 lvdd 47 mii_txd3 83 gpioa4 119 cfiowr# 12 moe# 48 mii_txd2 84 gpioa5 120 cfireq 13 mwe0# 49 mii_txd1 85 gpioa6 121 cfrst 14 mwe1# 50 lvdd 86 gpioa7 122 vss 15 hvdd1 51 mii_txd0 87 hvdd1 123 hvdd1 16 mclken 52 mii_txen 88 vss 124 cfwait# 17 mclk 53 mii_txclk 89 gpiob0 125 cfstschg# 18 vss 54 mii_rxer 90 gpiob1 126 cfden# 19 mras# 55 vss 91 gpiob2 127 cfddir 20 mcas# 56 hvdd1 92 gpiob3 128 ma0 21 md0 57 mii_rxclk 93 lvdd 129 ma1 22 md1 58 mii_rxdv 94 gpiob4 130 ma2 23 md2 59 mii_rxd0 95 gpiob5 131 ma3 24 md3 60 mii_rxd1 96 gpiob6 132 vss 25 vss 61 lvdd 97 gpiob7 133 lvdd 26 lvdd 62 mii_rxd2 98 vss 134 ma4 27 md4 63 mii_rxd3 99 cmhref 135 ma5 28 md5 64 mii_mdc 100 cmvref 136 ma6 29 md6 65 mii_mdio 101 cmclkin 137 ma7 30 md7 66 vss 102 cmclkout 138 ma8 31 hvdd1 67 clki 103 cmdata0 139 hvdd1 32 md8 68 pllvss 104 cmdata1 140 ma9 33 md9 69 vcp 105 hvdd2 141 ma10 34 md10 70 pllvdd 106 cmdata2 142 ma11 35 md11 71 reset# 107 cmdata3 143 ma12 36 vss 72 testen 108 cmdata4 144 ma13 note: # at the right end of a pin name indicates an low active signal. 73 108 37 72 36 1 144 109
S1S65010 4 epson ? pin description #: # at the right end of a pin nam e indicates an active low signal. i: input pin o: output pin io: bi-directional pin p: power supply cell type description cell type description applicable pin example ics lvcmos schmitt input tck, clki, reset# icd1 lvcmos input with pull down resistor (50k @3.3v) testen icu1 lvcmos input with pull up resistor (50k @3.3v) tms, tdi icsu1 lvcmos schmitt input with pull up resistor trst# blnc4 low noise lvcmos io buffer ( 4ma) mii blnc4u1 low noise lvcmos io buffer with pull-up resistor (50k @3.3v) ( 4ma) cf interface blnc4d2 low noise lvcmos io buffer with pull-down resistor (100k @3.3v) ( 4ma) md [15:0] blns4 low noise lvcmos schmitt io buffer ( 4ma) gpioa, gpiob, gpiod [1:0] blns4d1 low noise lvcmos schmitt io buffer with pull-down resistor (50k @3.0v) ( 4ma) camera interface oln4 low noise output buffer ( 4ma) memc interface (excluding md) otln4 low noise tri-state output buffer ( 4ma) tdo oltr low voltage transparent output vcp pin description pin name type cell type pin no. description (ma [23:22]) (i/o) (blns4) (97, 96) see gpiob[7:6] for more detail of these pins (ma [21:20]) (i/o) (blns4) (114-115) see gpiod[1:0] for more detail of these pins ma [19:12] o oln4 7, 1-5, 143-144 address outputs [19:12] out of these, ma[15:14] become ba[1:0] as a bank address, when using sdram. ma 11 o oln4 142 this pin has the following functions: x ma11: address output 11 (default pin function) x cfreg# output during the compactflash (cf) cy cles, this signal behaves as the reg# signal selecting attribute or i/o space of the cf card. ma [10:0] o oln4 128-131, 134-138, 140-141 these pins have the following functions: x ma[10:0]: address outputs [10:0] (default pin function) x cfaddr[10:0] outputs during the cf cycles, these signal s become the cf interface address signals [10:0]. md [15:0] i/o blnc4d2 21-24, 27-30, 32-35, 37-40 these pins have the following functions: x 16-bit data bus for memory (default pin function) x during the cf cycles, these pins become 16 bit data. x modesel[15:0] at the power on reset (reset# is changed from low to high), these pins are sampled to determi ne the internal operation mode. see ?system configuration by modesel pin? for more details. to determine the operation mode, a pull-up resistor may be required externally. (resistor value:4.7k - 10k range) mcs [2:0]# o oln4 8-10 chip select signals for memory (sdram and static memories) (low active) mcs2# is for sdram moe# o oln4 12 this pin has the fo llowing functions:(low active) x moe#: read strobe signal for memory read cycle (default pin function) x cfoe# output during the cf cycle, this signal becomes output enable signal for cf common memory or attribute space access.
S1S65010 epson 5 pin name type cell type pin no. description mwe0# o oln4 13 this pin has the fo llowing functions:(low active) x mwe0# : write enable signal for memory (for static memory) (default pin function) x cfwe# output during the cf cycle, this signal becomes write enable signal for cf common memory or attribute space access. mwe1# o oln4 14 write enable signal for memory (for sdram) (low active) mclk o oln4 17 clock output signal for sdram outputs the same frequency as the internal operating frequency (cpuclk). mclken o oln4 16 clock enable signal for sdram mras# o oln4 19 ras signal for sdram (low active) mcas# o oln4 20 cas signal for sdram (low active) mdqml mdqmh o oln4 41-42 these pins hav e the following functions: x byte enable signal (for static memory) x dqm signal for sdram mdqml and mdqmh correspond to lower byte and higher byte respectively. mii_txclk i/o blnc4 53 this pin has the following functions: x mii_txclk: clock txclk input for sending data from media independent interface ethernet phy (hereafter referred to as mii phy) (default pin function; select ?function 1?) x gpiof7 input/output mii_txen i/o blnc4 52 this pin has the following functions: x mii_txen: send output enable txen output to mii phy (default pin function; select ?function 1?) x gpiof6 input/output mii_txd3 i/o blnc4 47 this pin has the following functions: x mii_txd3: send data txd3 output to mii phy (default pin function; select ?function 1?) x gpiof2 input/output mii_txd2 i/o blnc4 48 this pin has the following functions: x mii_txd2: send data txd2 output to mii phy (default pin function; select ?function 1?) x gpiof3 input/output mii_txd1 i/o blnc4 49 this pin has the following functions: x mii_txd1: send data txd1 output to mii phy (default pin function; select ?function 1?) x gpiof4 input/output mii_txd0 i/o blnc4 51 this pin has the following functions: x mii_txd0: send data txd0 output to mii phy (default pin function; select ?function 1?) x gpiof5 input/output mii_rxclk i/o blnc4 57 this pin has the following functions: x mii_rxclk: receive data clock rxclk input from mii phy (default pin function; select ?function 1?) x gpiog1 input/output mii_col i/o blnc4 46 this pin has the following functions: x mii_col: collision col detection input from mii phy (default pin function; select ?function 1?) x gpiof1 input/output mii_crs i/o blnc4 45 this pin has the following functions: x mii_crs: carrier sense crs input from mii phy (default pin function; select ?function 1?) x gpiof0 input/output mii_rxdv i/o blnc4 58 this pin has the following functions: x mii_rxdv: receive data valid rxdv input from mii phy (default pin function; select ?function 1?) x gpiog2 input/output mii_rxd[3:0] i/o blnc4 59-60, 62-63 these pins have the following functions: x mii_rxd[3:0]: receive data rxd [3:0] input from mii phy (default pin function; select ?function 1?) x gpiog[6:3] input/output
S1S65010 6 epson pin name type cell type pin no. description mii_rxer i/o blnc4 54 this pin has the following functions: x mii_rxer: receive error rxer for mii phy (default pin function; select ?function 1?) x gpiog0 input/output mii_mdc i/o blnc4 64 this pin has the following functions: x mii_mdc: management interface clock mdc output for mii phy (default pin function; select ?function 1?) x gpiog7 input/output mii_mdio i/o blnc4 65 this pin has the following functions: x mii_mdio: management interface data mdio input/output for mii phy (default pin function; select ?function 1?) x gpioh0 input/output cmdata[7:0] i/o blns4d1 103-104, 106-111 these pins have the following functions: x cmdata[7:0]: yuv data from camera after reset, theses pins become gp ioc[7:0] input. to use as the cmdata[7:0] pin, select ?function 1? in the bit[15:0] of the gpioc pin function register. x gpioc[7:0] input/output (default pin function) cmvref i/o blns4d1 100 this pin has the following functions: x cmvref: vertical sync input from camera after reset, this pin becomes gpiod4 input. to use as the cmvref pin, select ?function 1? in the bit[9:8] of the gpiod pin function register. x gpiod4 input/output (default pin function) cmhref i/o blns4d1 99 this pin has the following functions: x cmhref: horizontal sync input from camera after reset, this pin becomes gpio d5 input. to use as the cmhref pin, select ?function 1? in the bi t [11:10] of the gpiod pin function register. x gpiod5 input/output (default pin function) cmclkout i/o blns4d1 102 this pin has the following functions: x cmclkout: basic clock output to camera after reset, this pin becomes gp iod6 input. to use as the cmclkout pin, select ?function 1? in the bit [13:12] of the gpiod pin function register. x gpiod6 input/output (default pin function) cmclkin i/o blns4d1 101 this pin has the following functions: x cmclkin: pixel clock input from camera after reset, this pin becomes gpiod7 input. to use as the cmclkin pin, select ?function 1? in the bi t [15:14] of the gpiod pin function register. x gpiod7 input/output (default pin function) cfce2# i/o blnc4u1 116 this pin has the following functions: x cfce2#: card enable 2 ce2# for compactflash card interface (hereafter referred to as cf) (low active) after reset, this pin becomes gpio d2 input. to use as the cfce2# pin, select ?function 1? in the bi t [5:4] of the gpiod pin function register. x gpiod2 input/output (default pin function) cfce1# i/o blnc4u1 117 this pin has the following functions: x cfce1#: card enable 1 ce1# for cf (low active) after reset, this pin becomes gpio d3 input. to use as the cfce1# pin, select ?function 1? in the bi t [7:6] of the gpiod pin function register. x gpiod3 input/output (default pin function) cfiord# i/o blnc4u1 118 this pin has the following functions: x cfiord#: io read strobe signal for cf (low active) after reset, this pin becomes gpioe0 input. to use as the cfiord# pin, select ?function 1? in the bi t [1:0] of the gpioe pin function register. x gpioe0 input/output (default pin function) x i2s0_sd: serial data for i2s0 (select ?function 2?)
S1S65010 epson 7 pin name type cell type pin no. description cfiowr# i/o blnc4u1 119 this pin has the following functions: x cfiowr#: io write strobe signal for cf (low active) after reset, this pin becomes gpioe1 input. to use as the cfiowr# pin, select ?function 1? in the bi t [3:2] of the gpioe pin function register. x gpioe1 input/output (default pin function) x i2s0_sck: serial clock for i2s0 (select ?function 2?) cfwait# i/o blnc4u1 124 this pin has the following functions: x cfwait#: wait request input from cf (low active) after reset, this pin becomes gpioe2 input. to use as the cfwait# pin, select ?function 1? in the bi t [5:4] of the gpioe pin function register. x mwait#: wait signal for memory controller (low active) uses the same pin with cfwa it# signal (select ?function 1?) x gpioe2 input/output (default pin function) cfrst i/o blnc4u1 121 this pin has the following functions: x cfrst: reset signal to cf card the signal is high when the card is reset and low when the card is under normal operation. after reset, this pin becomes gpio e3 input. to use as the cfrst pin, select ?function 1? in the bi t [7:6] of the gpioe pin function register. x gpioe3 input/output (default pin function) x i2s0_ws: word select for i2s0 (select ?function 2?) cfireq i/o blnc4u1 120 this pin has the following functions: x cfireq: interrupt request signal from cf card after reset, this pin becomes gpioe4 input. to use as the cfireq pin, select ?function 1? in the bi t [9:8] of the gpioe pin function register. x gpioe4 input/output (default pin function) cfstschg# i/o blnc4u1 125 this pin has the following functions: x cfstschg#: status change signal from cf card (low active) after reset, this pin becomes gp ioe5 input. to use as the cfstschg# pin, select ?function 1? in the bit [11:10] of the gpioe pin function register. x gpioe5 input/output (default pin function) x i2s1_sd: serial data for i2s1 (select ?function 2?) cfden# i/o blnc4u1 126 this pin has the following functions: x cfden#: cf data bus enable signal of cf card for external buffer (low active) after reset, this pin becomes gpioe6 input. to use as the cfden# pin, select ?function 1? in the bi t [13:12] of the gpioe pin function register. x gpioe6 input/output (default pin function) x i2s1_sck: serial clock for i2s1 (select ?function 2?) cfddir i/o blnc4u1 127 this pin has the following functions: x cfddir: data bus direction signal for cf when cf data is read, this pin becom es low. after reset, this pin becomes gpioe7 input. to use as the cfddir pin, select ?function 1? in the bit [15:14] of the gpioe pin function register. x gpioe7 input/output (default pin function) x i2s1_ws: word select for i2s1 (select ?function 2?) gpioa0 i/o blns4 79 this pin has the following functions: x gpioa0 input/output (default pin function) x txd0: uart send data output (select ?function 1?) gpioa1 i/o blns4 80 this pin has the following functions: x gpioa1 input/output (default pin function) x rxd0: uart receive data input (select ?function 1?) gpioa2 i/o blns4 81 this pin has the following functions: x gpioa2 input/output (default pin function) x spi_ss: chip select for spi (select ?function 1?) x txd1: uart lite send data output (select ?function 2?)
S1S65010 8 epson pin name type cell type pin no. description gpioa3 i/o blns4 82 this pin has the following functions: x gpioa3 input/output (default pin function) x spi_sclk: serial clock for spi (select ?function 1?) x rxd1: uart lite receive data input (select ?function 2?) gpioa4 i/o blns4 83 this pin has the following functions: x gpioa4 input/output (default pin function) x spi_miso: master in/slave out for spi (select ?function 1?) gpioa5 i/o blns4 84 this pin has the following functions: x gpioa5 input/output (default pin function) x spi_mosi: master out/slave in for spi (select ?function 1?) gpioa6 i/o blns4 85 this pin has the following functions: x gpioa6 input/output (default pin function) x scl: clock for i 2 c input/output (select ?function 1?) gpioa7 i/o blns4 86 this pin has the following functions: x gpioa7 input/output (default pin function) x sda: data for i 2 c input/output (select ?function 1?) gpiob0 i/o blns4 89 this pin has the following functions: x gpiob0 input/output (default pin function) x iint0 input x i2s0_ws: word select for i2s0 (select ?function 2?) gpiob1 i/o blns4 90 this pin has the following functions: x gpiob1 input/output (default pin function) x int1 input x rts0#: uart send request output (select ?function 1?) x i2s0_sck: serial clock for i2s0 (select ?function 2?) gpiob2 i/o blns4 91 this pin has the following functions: x gpiob2 input/output (default pin function) x int2 input x cts0#: uart sendable input (select ?function 1?) x i2s0_sd: serial data for i2s0 (select ?function 2?) gpiob3 i/o blns4 92 this pin has the following functions: x gpiob3 input/output (default pin function) x int3 input x timer0 output (select ?function 1?) x i2s1_sd: serial data for i2s1 (select ?function 2?) gpiob4 i/o blns4 94 this pin has the following functions: x gpiob4 input/output (default pin function) x int4 input x timer1 output (select ?function 1?) gpiob5 i/o blns4 95 this pin has the following functions: x gpiob5 input/output (default pin function) x int5 input x timer2 output (select ?function 1?) gpiob6 i/o blns4 96 this pin has the following functions: x gpiob6 input/output (default pin function) x int6 input x ma22: address output pin 22 (select ?function 1?) x i2s1_sck: serial clock for i2s1 (select ?function 2?) gpiob7 i/o blns4 97 this pin has the following functions: x gpiob7 input/output (default pin function) x int7 input x ma23: address output pin 23 (select ?function 1?) x i2s1_ws: word select for i2s1 (select ?function 2?) gpiod0 i/o blns4 114 this pin has the following functions: x gpiod0 input/output (default pin function) x int8 input x ma20: address output signal 20 (select ?function 1?) gpiod1 i/o blns4 115 this pin has the following functions: x gpiod1 input/output (default pin function) x ma21: address output signal 21 (select ?function 1?)
S1S65010 epson 9 pin name type cell type pin no. description clki i ics 67 32.768khz clock input basic clock input to this chip. th is clock is used as reference clock input for internal pll to generate system clock. this pin has a schmitt trigger input buffer. vcp o oltr 69 test pin for built-in pll this pin is used to monitor t he pll output when conducting a test. make this pin open for normal operation. trst# i icsu1 73 reset input for jtag interface (low active) this pin has a schmitt trigger i nput buffer with pull-up resistor. tck i ics 74 clock input pin for jtag interface this pin has a schmitt trigger input buffer. tms i icu1 75 tms pin for jtag interface this pin has a built-in pull-up resistor. tdi i icu1 76 serial data input pin for jtag interface this pin has a built-in pull-up resistor. tdo o otln4 77 serial data output pin for jtag interface testen i icd1 72 test enable (high active) this pin has a built-in pull-down resistor. connect this pin to vss or make it open for normal operation. reset# i ics 71 system reset signal (low active) even after hvdd1 and lvdd become stable at power on, keep reset# active (low) for 100ms. hvdd1 p p 15, 31, 43, 56, 87, 123, 139 power supply for i/o cell : 3.3v (excluding camera interface) hvdd2 p p 105 power supply for camera interface : 3.0 (typical) 2.4v (min.) - 3.6v (max.) lvdd p p 11, 26, 50, 61, 93, 113, 133 power supply for core (internal) : 1.8v pllvdd p p 70 power supply for analog (pll) : 1.8v it is necessary to handle this as an analog power supply. provides low noise and a stable power supply. pllvss p p 68 ground for analog (pll) it is necessary to handle this as an analog power supply. provide low noise and stable ground. vss p p 6, 18, 25, 36, 44, 55, 66, 78, 88, 98, 112, 122, 132 common ground for i/o cells, camera interface and core power supplies
S1S65010 10 epson ? system configuration by modesel pin value at resetting pin name pin function low high md0 modesel0 32khz mode reserved (for test) * md1 modesel1 crystal oscillation stable time(3 sec) reserved (for test) * md2 modesel2 normal operation reserved (for test) * md3 modesel3 reserved (use ?0.?) md4 modesel4 for user setting for user setting md5 modesel5 for user setting for user setting md6 modesel6 for user setting for user setting md7 modesel7 for user setting for user setting md8 modesel8 for user setting for user setting md9 modesel9 for user setting for user setting md10 modesel10 for user setting for user setting md11 modesel11 for user setting for user setting md12 modesel12 for user setting for user setting md13 modesel13 for user setting for user setting md14 modesel14 for user setting for user setting md15 modesel15 for user setting for user setting * note : do not configure the system using the ?reserved (for test )? value. ic may be damaged. ? physical specification item features core system power supply (lvdd) 1.8v 0.15v i/o system power supply (hvdd1) 3.3v 0.30v camera interface power supply (hvdd2) 2.4v (min.) - 3.6v (max.) power supply pll power supply (pllvdd) 1.8v 0.15v (analog power supply) operating frequency cpu 50mhz max. power consumption (reference value) 140mw (typ.), 3mw (when the status is ha lt and mii interface stopped) operative temperature t a = -40 to +85 c package tqfp 144 pin (tqfp24) 16 16 1 mm / 0.4mm pin pitch
S1S65010 epson 11 ? multiplex pin function of gpio pin and pin function after reset S1S65010 pin name pin function after reset gpio int address bus uart/ uart lite i 2 c spi / i 2 s timer camera interface cf card mii gpioa0 gpioa0 gpioa0 txd0 gpioa1 gpioa1 gpioa1 rxd0 gpioa2 gpioa2 gpioa2 txd1 spi_ss gpioa3 gpioa3 gpioa3 rxd1 spi_sclk gpioa4 gpioa4 gpioa4 spi_miso gpioa5 gpioa5 gpioa5 spi_mosi gpioa6 gpioa6 gpioa6 scl gpioa7 gpioa7 gpioa7 sda gpiob0 gpiob0 gpiob0 int0 i2s0_ws gpiob1 gpiob1 gpiob1 int1 rts0# i2s0_sck gpiob2 gpiob2 gpiob2 int2 cts0# i2s0_sd gpiob3 gpiob3 gpiob3 int3 i2s1_sd timer0out gpiob4 gpiob4 gpiob4 int4 timer1out gpiob5 gpiob5 gpiob5 int5 timer2out gpiob6 gpiob6 gpiob6 int6 ma22 i2s1_sck gpiob7 gpiob7 gpiob7 int7 ma23 i2s1_ws cmdata0 gpioc0 gpioc0 cmdata0 cmdata1 gpioc1 gpioc1 cmdata1 cmdata2 gpioc2 gpioc2 cmdata2 cmdata3 gpioc3 gpioc3 cmdata3 cmdata4 gpioc4 gpioc4 cmdata4 cmdata5 gpioc5 gpioc5 cmdata5 cmdata6 gpioc6 gpioc6 cmdata6 cmdata7 gpioc7 gpioc7 cmdata7 gpiod0 gpiod0 gpiod0 int8 ma20 gpiod1 gpiod1 gpiod1 ma21 cfce2# gpiod2 gpiod2 cfce2# cfce1# gpiod3 gpiod3 cfce1# cmvref gpiod4 gpiod4 cmvref cmhref gpiod5 gpiod5 cmhref cmclkout gpiod6 gpiod6 cmclkou t cmclkin gpiod7 gpiod7 cmclkin cfiord# gpioe0 gpioe0 i2s0_sd cfiord# cfiowr# gpioe1 gpioe1 i2s0_sck cfiowr# cfwait# gpioe2 gpioe2 cfwait# / mwait# cfrst gpioe3 gpioe3 i2s0_ws cfrst cfireq gpioe4 gpioe4 cfireq cfstschg# gpioe5 gpioe5 i2s1_sd cfstschg# cfden# gpioe6 gpioe6 i2s1_sck cfden# cfddir gpioe7 gpioe7 i2s1_ws cfddir mii_crs mii_crs gpiof0 mii_crs mii_col mii_col gpiof1 mii_col mii_txd3 mii_txd3 gpiof2 mii_txd3 mii_txd2 mii_txd2 gpiof3 mii_txd2 mii_txd1 mii_txd1 gpiof4 mii_txd1 mii_txd0 mii_txd0 gpiof5 mii_txd0 mii_txen mii_txen gpiof6 mii_txen mii_txclk mii_txclk gpiof7 mii_txclk mii_rxer mii_rxer gpiog0 mii_rxer mii_rxclk mii_rxclk gpiog1 mii_rxclk mii_rxdv mii_rxdv gpiog2 mii_rxdv mii_rxd0 mii_rxd0 gpiog3 mii_rxd0 mii_rxd1 mii_rxd1 gpiog4 mii_rxd1 mii_rxd2 mii_rxd2 gpiog5 mii_rxd2 mii_rxd3 mii_rxd3 gpiog6 mii_rxd3 mii_mdc mii_mdc gpiog7 mii_mdc mii_mdio mii_mdio gpioh0 mii_mdio function 2 function 1 : function 1 : function 2
S1S65010 12 epson ? status of pin during reset and after reset pin name i/o direction during reset level during reset built-in resistances description ma[19:0] output low (however, only bit11 is high.) none md[15:0] input low pull-down resistance 100k mcs[2]# output low none mcs[1]# output high none mcs[0]# output high none moe# output high none mwe0# output high none mwe1# output low none mclk output mclk(32khz) none mclken output high none mras# output low none mcas# output high none mdqml output low none mdqmh output low none mii_txclk input high-z none depends on exte rnal circuitry (normally mii-phy) mii_txen output low none mii_txd[3:0] output undefined none undefined until initialized mii_rxclk input high-z none depends on exte rnal circuitry (normally mii-phy) mii_col input high-z none depends on exte rnal circuitry (normally mii-phy) mii_crs input high-z none depends on exte rnal circuitry (normally mii-phy) mii_rxdv input high-z none depends on exte rnal circuitry (normally mii-phy) mii_rxd[3:0] input high-z none depends on ex ternal circuitry (normally mii-phy) mii_rxer input high-z none depends on exte rnal circuitry (normally mii-phy) mii_mdc output low none mii_mdio input high-z none depends on exte rnal circuitry (normally mii-phy) cmdata[7:0] input low pull-down resistance 50k cmvref input low pull-down resistance 50k cmhref input low pull-down resistance 50k cmclkout input low pull-down resistance 50k cmclkin input low pull-down resistance 50k cfce2# input high pull-up resistance 50k cfce1# input high pull-up resistance 50k cfiord# input high pull-up resistance 50k cfiowr# input high pull-up resistance 50k cfwait# input high pull-up resistance 50k cfrst input high pull-up resistance 50k cfireq input high pull-up resistance 50k cfstschg# input high pull-up resistance 50k cfden# input high pull-up resistance 50k cfddir input high pull-up resistance 50k gpioa[7:0] input high-z none depends on external circuitry gpiob[7:0] input high-z none depends on external circuitry gpiod[1:0] input high-z none depends on external circuitry clki input high-z none vcp output high-z none leave open trst# input high pull-up resistance 50k tck input high-z none tms input high pull-up resistance 50k tdi input high pull-up resistance 50k tdo output high-z none testen input low pull-down resistance 50k reset# input low none the following reset value is decided depending on the content of each pin set.
S1S65010 epson 13 ? usage example S1S65010 flash rom eeprom camera module audio module phy pulse transformer protocol stack mac address (option) image memory and cpu work memory rj45 10base-t/ 100base-tx a udio input/output image capture i 2 s 32.768khz ethernet lan card osc osc 25mhz infrared sensor camera control triggered by movement trigger i 2 c sdram/ sram
S1S65010 seiko epson corporation ic sales department ic international sales gloup 421-8 hino, hino-shi, tokyo 191-8501, japan phone: 042-587-5814 fax: 042-587-5117 notice: no part of this material may be reproduced or duplicated in any fo rm or by any means without the written permission of seiko ep son. seiko epson reserves the right to make c hanges to this material without notice. se iko epson does not assume any liability of a ny kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, furt her, there is no representation that this material is app licable to products requiring high level reliab ility, such as, medical products. moreo ver, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that any thing made in accordance with this material will be free from any patent or copy right infringement of a third party. this material or portio ns thereof may contain technology or the subject relati ng to strategic products under the control of the foreign exchange and foreign trade la w of japan and may require an export license from the ministry of economy, trade and industry or other approval from another government ag ency. is a registered trademark of arm. compactflash is a registered trademark of sandisk. all other product names mentioned herein are trademarks and/or registered trademarks of t heir respective companies. ?seiko epson corporation 2008, all rights reserved. document code: 405099104 first issue june, 2004 printed june, 2008 in japan ? epson electronic devices website http://www.epson.jp/device/semicon_e/

▲Up To Search▲

Price & Availability of S1S65010

	To Download S1S65010 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .